(1) Field of the invention
The present invention relates to a circuit structure of a fuzzy logic controller (FLC) or a fuzzy control processor and particularly to a structure of a memory circuit of the fuzzy logic controller and its data processing technique.
(2) Description of the background art
A previously proposed fuzzy logic controller (FLC) is exemplified by a recorded paper called--M. Togai and H. Watanabe, Proceeding 2nd Conference on AI Application IEEE, 192/197 1985.
The disclosed fuzzy logic controller (FLC) includes first MIN logic elements each of which inputs one of input membership functions A.sub.1 .about.A.sub.N and observed quantity A', first MAX logic elements which calculate matchings .alpha..sub.1 .about..alpha..sub.N, second MIN logic elements each of which inputs one of output membership functions B.sub.1 .about.B.sub.N and one of the matchings .alpha..sub.1 .about..alpha..sub.N, a second MAX logic element which generalizes each conclusion derived by the second MIN logic element, and a defuzzifier which makes a decision of a specific operating variable V*.
A theoretical explanation of fuzzy inference used in the previously proposed fuzzy logic controller will be made as follows:
As shown in FIG. 1, suppose the following fuzzy logic linguistic rule. EQU IF u=A.sub.i THEN v=B.sub.i ( 1).
In the rule of (1), A.sub.i and B.sub.i denote fuzzy quantities and may be words such as large , medium , or small or alternatively be approximate numerical values such as approximately five. In the fuzzy inference, these fuzzy words and fuzzy numerical values are accordingly made to correspond to their membership functions as shown in a bottom part of FIG. 1. In a table of FIG. 1, each lateral axis denotes an input ranges of u or v (in terms of angles, for example, 0.degree..about.180.degree.) and each longitudinal axis denotes a magnitude (grade) by which the value of u or v belongs to a set of A.sub.i. Then, the grade 1 is an input that any person can perceive large or small . As appreciated from FIG. 1, an intermediate grade is provided.
When the input is given in the form of the membership function as u=A', the fuzzy logic controller described above calculates as follows: A'.andgate.A.sub.i (provided that .andgate. denotes a minimum value logic), and thereafter derives .orgate. (A'.andgate.A.sub.i)=.alpha..sub.i. .orgate. denotes a maximum value logic. .alpha..sub.i denotes a degree of matching for the i number of rule and indicates how degrees the corresponding rule has an effect. For example, if .alpha..sub.i =0.5, the degree of matching to which a conclusion of the rule is matched is half, i.e., it is not known well. Next, .alpha..sub.i .andgate.B.sub.i, i.e., a head portion of a conclusion portion of an area of B.sub.i is cut out. Since the rule is not applied only to .alpha..sub.i, the conclusion portion is clamped by .alpha..sub.i. As described above, since the conclusions of the respective rules are derived in the form of the output membership functions, the conclusions are generalized by calculating .orgate. (.alpha..sub.i .andgate.B.sub.i). Since a logic of OR serves to connect between the rules, the logic of OR in the fuzzy inference is calculated, i.e., .orgate. (maximum value logic) is carried out. Thus, the conclusion of B' is derived in the form of the output membership function. However, this indicates the degrees of the respective output values. Therefore, if, e.g., a weight center of the output membership function of B' is derived to output a final operating variable V*. In this way, in the fuzzy logic control the operating variable V* can be derived by generally inferring the fuzzy control result on the basis of a plurality of control linguistic rules according to the input A'.
The above-described fuzzy inference operation is described similarly in an English literature titled "A VLSI Fuzzy Logic Controller with Reconfigurable, Cascadable Architecture" by Hiroyuki Watanabe, Wayne D. Dettloff, and Kathy E Yount in IEEE Journal On Solid-State Circuits, Vol. 25, No. 2, on April, 1990.
In details, the fuzzy logic operators .orgate., .andgate. are provided in the form of hardware in the MIN logic elements and the MAX logic elements. Each membership function is stored in a memory circuit of the fuzzy logic controller and is read out at an appropriate timing to be transmitted to the respective logic elements. In the example described above, the membership functions are serially accessed. Although a memory capacity may be minimized, a speed of executing the fuzzy inferences becomes remarkably reduced as the number of rules are increased.
An English literature of IEEE CICC, 12.4.1-12.4.5, 1989 by W. D. Dettloff, K. E. Yount, and H. Watanabe exemplifies specific structures of fuzzy logic, defuzzifier, and MIN logic calculation unit.
The above-identified English literature titled "A VLSI Fuzzy Logic Controller with Reconfigurable, Cascadable Architecture" by Hiroyuki Watanabe, Wayne D. Dettloff, and Kathy E Yount in IEEE Journal On Solid-State Circuits, Vol. 25, No. 2, on April, 1990 also exemplifies the same specific structures described above.
In the specific structures disclosed in the latter literature, the membership functions are parallel accessed until 102 rule and high speed inference can be executed. However, the memory capacity becomes large such that about 70% of a chip area is occupied.
Problems raised in the previously proposed fuzzy logic controllers will be explained below.
First, it is necessary to provide a considerably large capacity of memory circuit in order to memorize the plurality of membership functions (in arbitrary forms).
For example, suppose that the number of input variables x.sub.i are three, the number of output variables y.sub.i are two, and the number of fuzzy logic linguistic rules are 20 and these variables and functions are stored in a single of the memory circuit. In this case, 100 numbers of membership functions are needed. If the single membership function is represented by 2.sup.8 .times.8 bits, the memory capacity required is totally calculated as 2.sup.8 .times.8.times.100. That is to say, 200 K bit RAM (Random Access Memory) is required.
In the case of the specific structure of rule logic disclosed in the above-identified English literature, about 0.48 million number of transistors (about 70%) from among about 0.69 million number of transistors on the single IC chip are provided as a memory unit. On the other hand, if the memory unit is provided as an external side of the IC chip, an overhead in access occurs and the fuzzy inference speed becomes remarkably slow.
In addition, if a resolution per single membership function is reduced, a quantization error may become remarkable depending on the contents of control although the memory capacity becomes decreased.
Next, if the fuzzy inference calculation portion (Rule logic) is configured in the parallel processing type, the circuit shown in the above-identified English literature needs to be arranged in parallel and the circuit scale becomes large. The rule logic described above is in a unit of four bits. If a larger resolution is required, the circuit scale becomes large so that the large scale rule logic cannot be put into practice in the viewpoint of consumed power and yield.
As described above, it is essential to eliminate the various problems in order to integrate the fuzzy logic controller into the practical IC chip. In the type of bit-serial processing of the rule logic shown in the above-identified English literature, the fuzzy inference speed becomes slow as the number of rules is increased. Consequently, an advantage of manufacturing an exclusive use chip (self-contained chip) becomes reduced.